Espressif Systems /ESP32-S3 /RTC_CNTL /OPTIONS0

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Interpret as OPTIONS0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SW_STALL_APPCPU_C0 0SW_STALL_PROCPU_C0 0 (SW_APPCPU_RST)SW_APPCPU_RST 0 (SW_PROCPU_RST)SW_PROCPU_RST 0 (BB_I2C_FORCE_PD)BB_I2C_FORCE_PD 0 (BB_I2C_FORCE_PU)BB_I2C_FORCE_PU 0 (BBPLL_I2C_FORCE_PD)BBPLL_I2C_FORCE_PD 0 (BBPLL_I2C_FORCE_PU)BBPLL_I2C_FORCE_PU 0 (BBPLL_FORCE_PD)BBPLL_FORCE_PD 0 (BBPLL_FORCE_PU)BBPLL_FORCE_PU 0 (XTL_FORCE_PD)XTL_FORCE_PD 0 (XTL_FORCE_PU)XTL_FORCE_PU 0XTL_EN_WAIT 0 (XTL_FORCE_ISO)XTL_FORCE_ISO 0 (PLL_FORCE_ISO)PLL_FORCE_ISO 0 (ANALOG_FORCE_ISO)ANALOG_FORCE_ISO 0 (XTL_FORCE_NOISO)XTL_FORCE_NOISO 0 (PLL_FORCE_NOISO)PLL_FORCE_NOISO 0 (ANALOG_FORCE_NOISO)ANALOG_FORCE_NOISO 0 (DG_WRAP_FORCE_RST)DG_WRAP_FORCE_RST 0 (DG_WRAP_FORCE_NORST)DG_WRAP_FORCE_NORST 0 (SW_SYS_RST)SW_SYS_RST

Description

RTC common configure register

Fields

SW_STALL_APPCPU_C0

{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU

SW_STALL_PROCPU_C0

{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU

SW_APPCPU_RST

APP CPU SW reset

SW_PROCPU_RST

PRO CPU SW reset

BB_I2C_FORCE_PD

BB_I2C force power down

BB_I2C_FORCE_PU

BB_I2C force power up

BBPLL_I2C_FORCE_PD

BB_PLL _I2C force power down

BBPLL_I2C_FORCE_PU

BB_PLL_I2C force power up

BBPLL_FORCE_PD

BB_PLL force power down

BBPLL_FORCE_PU

BB_PLL force power up

XTL_FORCE_PD

crystall force power down

XTL_FORCE_PU

crystall force power up

XTL_EN_WAIT

wait bias_sleep and current source wakeup

XTL_FORCE_ISO

No public

PLL_FORCE_ISO

No public

ANALOG_FORCE_ISO

No public

XTL_FORCE_NOISO

No public

PLL_FORCE_NOISO

No public

ANALOG_FORCE_NOISO

No public

DG_WRAP_FORCE_RST

digital wrap force reset in deep sleep

DG_WRAP_FORCE_NORST

digital core force no reset in deep sleep

SW_SYS_RST

SW system reset

Links

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